AMD Eight-Core Bulldozer CPU Cache is 77% bigger Vs Six-Core

The eight-core microprocessors from Advanced Micro Devices based on the Bulldozer micro-architecture that feature Orochi design will get massive internal cache systems compared to current-generation of chips. In total, the top-of-the-range single-die processor will have 16MB of cache.

AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.

 

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X-Bit labs reports:
AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.
Large L2 caches will help AMD's next-generation microprocessors to ensure higher performance in single-threaded applications compared to today's multi-core chips that only have 512KB of L2, whereas massive L3 cache will maximize memory bandwidth. In both cases this will bring notable performance gains compared to today's Stars/Greyhound architecture.
AMD Orochi design is the company's next-generation processor for high-end desktop and server markets. The chip will feature eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have shared L3 cache, new dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Orochi chips will use new AM3+ form-factor and will require brand new platforms [via xbitlabs].